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15/05/2025
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Implemente a lógica abaixo onde cada componente é um componente
-- compnt.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY compnt IS
PORT (IN1 : IN std_logic;
IN2 : IN std_logic;
SAIDA : OUT std_logic);
END compnt;
ARCHITECTURE funcao OF compnt IS
COMPONENT porta_inversora IS
PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC);
END COMPONENT;
COMPONENT porta_and IS
PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END COMPONENT;
SIGNAL X: STD_LOGIC;
BEGIN
U1: porta_inversora PORT MAP (IN1,X);
U2: porta_and PORT MAP (X,IN2,SAIDA);
END funcao;-- porta_inversora.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY porta_inversora IS
PORT (a: IN STD_LOGIC;
b: OUT STD_LOGIC);
END porta_inversora;
ARCHITECTURE funcao OF porta_inversora IS
BEGIN
b<=NOT a;
END funcao;-- porta_and.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY porta_and IS
PORT (a, b: IN STD_LOGIC;
c: OUT STD_LOGIC);
END porta_and;
ARCHITECTURE funcao OF porta_and IS
BEGIN
c <= a and b;
END funcao;Faça o circuito abaixo utilizando PACKAGE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY compnt IS
PORT (in1, in2, in3, in4 : IN std_logic;
x, y : OUT std_logic);
END compnt;
ARCHITECTURE funcao OF compnt IS
COMPONENT porta_inversora IS
PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC);
END COMPONENT;
COMPONENT porta_and IS
PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END COMPONENT;
COMPONENT porta_and_3 IS
PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC);
END COMPONENT;
SIGNAL not_in2: STD_LOGIC;
BEGIN
U1: porta_inversora PORT MAP (in2,not_in2);
U2: porta_and PORT MAP (in1,in2,x);
U3: porta_and_3 PORT MAP (not_in2,in3,in4,y);
END funcao;LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY porta_and_3 IS
PORT (a, b, c: IN STD_LOGIC;
d: OUT STD_LOGIC);
END porta_and_3;
ARCHITECTURE funcao OF porta_and_3 IS
BEGIN
d <= (a and b) and c;
END funcao;
-- compnt.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
USE work.componentes_circuito.all;
ENTITY compnt IS
generic (n: integer := 2);
PORT (
input: in bit_vector (n downto 0);
output: out bit_vector (n+1 downto 0)
);
END compnt;
ARCHITECTURE funcao OF compnt IS
BEGIN
U1: parity_generator generic map (n) port map (input, output);
END funcao;-- parity_generator.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY parity_generator IS
generic(n: integer := 7);
PORT (
input: in bit_vector (n downto 0);
output: out bit_vector (n+1 downto 0)
);
END parity_generator;
ARCHITECTURE funcao OF parity_generator IS
BEGIN
process (input)
variable temp1: bit;
variable temp2: bit_vector(output'range);
begin
temp1 := '0';
for i in input'range loop
temp1 := temp1 xor input (i);
temp2(i) := input(i);
end loop;
temp2(output'high) := temp1;
output <= temp2;
end process;
END funcao;-- componentes_circuito.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE componentes_circuito IS
---------- PARITY_GEN -----------
COMPONENT parity_generator IS
generic (n: positive);
PORT (
input: IN bit_vector(n downto 0);
output: out bit_vector(n+1 downto 0)
);
END COMPONENT;
END componentes_circuito;