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23/04/2025
Publico
Exercício 1: Projete um FF do tipo D, com clock na borda de subida e sinal de reset assíncrono (quando rst = ‘1’, a saída vai a zero).
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ifthen IS
PORT (d, clk, rst: in std_logic;
q: out std_logic);
END ifthen;
ARCHITECTURE logica OF ifthen IS
BEGIN
process (clk, rst)
begin
if (rst = '1') then
q <= '0';
else
if (clk'event and clk = '1') then
q <= d;
end if;
end if;
end process;
END logica; my_s <= a nand b;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ifthen IS
PORT (a,b, clk, rst: in std_logic;
q: out std_logic);
END ifthen;
ARCHITECTURE logica OF ifthen IS
signal my_s: std_logic;
BEGIN
my_s <= a nand b;
process (clk, rst)
begin
if (rst = '1') then
q <= '0';
else
if (clk'event and clk = '1') then
q <= my_s;
end if;
end if;
end process;
END logica;LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ifthen IS
PORT (clk: in std_logic;
a,b: in integer range 3 downto 0;
reg_comp: out std_logic;
reg_sum: out integer range 4 downto 0
);
END ifthen;
ARCHITECTURE logica OF ifthen IS
signal comp: std_logic;
signal sum: integer range 4 downto 0;
BEGIN
comp <= '1' when a > b else '0';
sum <= a + b;
process (clk)
begin
if (clk'event and clk = '1') then
reg_comp <= comp;
reg_sum <= sum;
end if;
end process;
END logica;LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ifthen IS
PORT (clk, serial: in std_logic;
q: out std_logic_vector (3 downto 0)
);
END ifthen;
ARCHITECTURE logica OF ifthen IS
signal reg: std_logic_vector (3 downto 0);
BEGIN
process (clk)
begin
if (clk'event and clk = '1') then
reg(3) <= serial;
reg(2) <= reg(3);
reg(1) <= reg(2);
reg(0) <= reg(1);
q(3) <= reg(3);
q(2) <= reg(2);
q(1) <= reg(1);
q(0) <= reg(0);
end if;
end process;
END logica;