Exemplo de simulação:

gerador_sim.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY gerador_sim IS
    PORT (
        sig1, sig2, y : IN std_logic;
        x : OUT std_logic
    );
END gerador_sim;

ARCHITECTURE logica OF gerador_sim IS
BEGIN
    WITH y SELECT 
        x <= sig1 xor sig2 when '0',
        sig1 xnor sig2 when others;
END ARCHITECTURE;

tb_gerador_sim.vhd

library IEEE;
use IEEE.std_logic_1164.all;
entity testbench2 is end;


architecture tb_gerador_sim of testbench2 is
component gerador_sim
    port(
        sig1, sig2, y : in std_logic;
        x : out std_logic
    );
end component;

signal sig_1, sig_2, y_1 : std_logic;

Begin
    funcao: gerador_sim port map (sig1 => sig_1, sig2 => sig_2, y => y_1, x => open);

    PROCESS
    BEGIN
        --signal sig1:--
        sig_1 <= '1';
        WAIT FOR 25 ns; sig_1 <= '0';
        WAIT FOR 50 ns;
    END PROCESS;

    PROCESS
    BEGIN
        --signal sig2:--
        sig_2 <= '1';
        WAIT FOR 25 ns; sig_2 <= '0';
        WAIT FOR 50 ns; sig_2 <= '1';
        WAIT FOR 25 ns; sig_2 <= '0';
        WAIT FOR 25 ns; sig_2 <= '1';
        WAIT FOR 50 ns; sig_2 <= '0';
        WAIT FOR 25 ns;
    END PROCESS;

    PROCESS
    BEGIN
        --signal y:--
        y_1 <= '1';
        WAIT FOR 20 ns; y_1 <= '0';
        WAIT FOR 10 ns; y_1 <= '1';
        WAIT FOR 10 ns; y_1 <= '0';
        WAIT FOR 40 ns;
    END PROCESS;

END tb_gerador_sim;

resultado