Exercício 1

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY estados IS
    PORT (
        clk : IN std_logic;
        saida: out std_logic_vector(1 downto 0)
    );
END estados;

ARCHITECTURE logica OF estados IS
type MEUS_ESTADOS is (A,B,C,D);
signal state: MEUS_ESTADOS;

BEGIN
    process (clk)
    begin
        if (clk'event and clk='1') then
            case state is
                when A  =>
                    saida <= "01";
                    state <= B;
                when B =>
                    saida <= "10";
                    state <= C;
                when C  =>
                    saida <= "11";
                    state <= D;
                when D =>
                    saida <= "00";
                    state <= A;
            end case;
        end if;
    end process;
END logica;

Exercício 2

Também é possível desacoplar a saída dos estados para outro process

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY estados IS
    PORT (
        clk : IN std_logic;
        saida: out std_logic_vector(1 downto 0)
    );
END estados;

ARCHITECTURE logica OF estados IS
type MEUS_ESTADOS is (A,B,C,D);
signal state: MEUS_ESTADOS;

BEGIN
    process (clk)
    begin
        if (clk'event and clk='1') then
            case state is
                when A => state <= B;
                when B => state <= C;
                when C => state <= D;
                when D => state <= A;
            end case;
        end if;
    end process;
    
    process (state)
    begin
        case state is
                when A => saida <= "01";
                when B => saida <= "10";
                when C => saida <= "11";
                when D => saida <= "00";
            end case;
    end process;
END logica;

Exercício 3

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY estados IS
    PORT (
        KEY: in std_logic_vector(0 to 1);
        SWITCH: in std_logic_vector(0 to 0);
        LED: out std_logic_vector(0 to 1)
    );
END estados;

ARCHITECTURE logica OF estados IS
type MEUS_ESTADOS is (A,B,C,D);
signal state: MEUS_ESTADOS;

signal clk, reset, dir: std_logic;
signal saida: std_logic_vector(0 to 1);


BEGIN
    clk <= key(0);
    reset <= key(1);
    dir <= SWITCH(0);
    LED <= saida;

    process (clk, reset, dir)
    begin
        if (clk'event and clk='1') then
            if (reset = '0') then
                state <= A;
            else
                if (dir = '1') then
                    case state is
                        when A => 
                            state <= B;
                        when B => 
                            state <= C;
                        when C => 
                            state <= D;
                        when D => 
                            state <= A;
                    end case;
                else
                    case state is
                        when A => 
                            state <= D;
                        when B => 
                            state <= A;
                        when C => 
                            state <= B;
                        when D => 
                            state <= C;
                    end case;
                end if;
            end if;
        end if;
    end process;
    
    process (state)
    begin
        case state is
                when A => saida <= "00";
                when B => saida <= "01";
                when C => saida <= "10";
                when D => saida <= "11";
            end case;
    end process;
END logica;

Exercício 4

Faça uma máquina de estados MOORE que controle a movimentação de um motor de passos (passo completo 1) com controle do sentido de rotação. Use clock 50MHz para clk (0,5 Hz), e DIP [0] para a direção. Como saída use LED [0-3]. Faça pelo modelo 2.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY estados IS
    PORT (
        SWITCH: in std_logic_vector(0 to 0);
        CLOCK_50: in std_logic;
        LED: out std_logic_vector(0 to 3)
    );
END estados;

ARCHITECTURE logica OF estados IS
type MEUS_ESTADOS is (A,B,C,D);
signal state: MEUS_ESTADOS;

signal dir: std_logic;
signal saida: std_logic_vector(0 to 3);


BEGIN
    dir <= SWITCH(0);
    LED <= saida;
    
    process (clock_50, dir)    
        variable clk : std_logic := '1';
        variable contador : natural range 0 to 10;
    begin
        if rising_edge(clock_50) then
            contador := contador + 1;
            if contador = 10 then
                contador := 0;
                clk := not clk;
            end if;
        end if;
        
        if (clk'event and clk='1') then
            if (dir = '1') then
                case state is
                    when A => 
                        state <= B;
                    when B => 
                        state <= C;
                    when C => 
                        state <= D;
                    when D => 
                        state <= A;
                end case;
            else
                case state is
                    when A => 
                        state <= D;
                    when B => 
                        state <= A;
                    when C => 
                        state <= B;
                    when D => 
                        state <= C;
                end case;
            end if;
        end if;
    end process;
    
    process (state)
    begin
        case state is
                when A => saida <= "1100";
                when B => saida <= "0110";
                when C => saida <= "0011";
                when D => saida <= "1001";
            end case;
    end process;
END logica;

Contem erro