Sem descrição.
16/04/2025
Publico
library ieee;
use ieee.std_logic_1164.all;
entity aula_logica is
port (
d: in std_logic_vector (0 to 4);
y: out std_logic);
end entity;
architecture funcao of aula_logica is
signal aux: std_logic_vector (0 to 3);
begin
aux(0) <= d(0) xor d(1);
gen: for i in 1 to 3 generate
aux(i) <= aux(i-1) xor d(i+1);
end generate gen;
y <= aux(3);
end funcao;
library ieee;
use ieee.std_logic_1164.all;
entity aula_logica is
port (
d: in std_logic_vector (0 to 5);
s: out std_logic);
end entity;
architecture funcao of aula_logica is
signal aux: std_logic_vector (0 to 4);
begin
aux(0) <= (d(0) and d(1)) or (d(1) and d(2));
gen: for i in 1 to 4 generate
aux(i) <= aux(i-1) xor d(i+1);
end generate gen;
s <= aux(4);
end funcao;Faça um código que tenha uma entrada e uma saída de 4 bits. A saída deve ser igual à entrada, com exceção do bit mais significativo que deve ser sempre ‘0’.
library ieee;
use ieee.std_logic_1164.all;
entity aula_logica is
port (
d: in std_logic_vector (0 to 4);
s: out std_logic_vector (0 to 4)
);
end entity;
architecture funcao of aula_logica is
begin
gen: for i in 1 to 4 generate
if_first: if i = 0 generate
s(i) <= '0';
end generate if_first;
if_others: if i /= 0 generate
s(i) <= d(i);
end generate if_others;
end generate gen;
end funcao;
library ieee;
use ieee.std_logic_1164.all;
entity aula_logica is
port (
b: in std_logic_vector (3 downto 0);
g: out std_logic_vector (3 downto 0)
);
end entity;
architecture funcao of aula_logica is
begin
gen: for i in 0 to 3 generate
if_first: if i = 0 generate
g(i) <= b(i);
end generate if_first;
if_others: if i /= 0 generate
g(i) <= b(i-1) xor b(i);
end generate if_others;
end generate gen;
end funcao;