Sem descrição.
17/04/2025
Publico
library ieee;
use ieee.std_logic_1164.all;
entity aulab is
port (
d, clk, rst: in std_logic;
q_guarded, q: out std_logic
);
end entity;
architecture funcao of aulab is
begin
bloco1: block (clk = '1')
begin
q_guarded <= guarded '0' when rst='1' else d;
q <= d;
end block bloco1;
end funcao;library ieee;
use ieee.std_logic_1164.all;
entity aulab is
port (
d, clk, rst: in std_logic;
q_guarded, q: out std_logic
);
end entity;
architecture funcao of aulab is
begin
bloco1: block (clk'event and clk='1') -- Detecção no evento de borda de subida
begin
q_guarded <= guarded '0' when rst='1' else d;
q <= d;
end block bloco1;
end funcao;
library ieee;
use ieee.std_logic_1164.all;
entity aulab is
port (
en: in std_logic;
a: in std_logic_vector(1 downto 0);
y: out std_logic_vector(0 to 3)
);
end entity;
architecture funcao of aulab is
begin
bloco1: block (en='1')
begin
y(0) <= guarded '1' when a = "00" else '0';
y(1) <= guarded '1' when a = "01" else '0';
y(2) <= guarded '1' when a = "10" else '0';
y(3) <= guarded '1' when a = "11" else '0';
end block bloco1;
end funcao;Faça o meio somador com saídas Tristate abaixo, sendo que, quando T= ‘1’, a saída do tristate é igual à entrada, e quando T=‘0’ a saída é de alta impedância. O bloco “meio somador” é ativado por um pino de enable.
library ieee;
use ieee.std_logic_1164.all;
entity aulab is
port (
a, b, e, t: in std_logic;
sum, carry_out: out std_logic
);
end entity;
architecture funcao of aulab is
begin
bloco1: block (e='1')
begin
sum <= guarded 'Z' when T = '0' else (a xor b);
carry_out <= guarded 'Z' when T = '0' else (a and b);
end block bloco1;
end funcao;