Configuração

DE0

• Device Family: Cyclone IV E
• Placa: EP4CE22F17C6.
• Simulation: ModelSim-Altera
  • VHDL

DE1-SoC-ALTERA

• Device Family: Cyclone V
• Placa: 5CSEMA5F31C6.
• Simulation: ModelSim-Altera
  • VHDL

Código base

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nome_projeto IS
    PORT (IN1 : IN std_logic;
        IN2 : IN std_logic;
        SAIDA : OUT std_logic);
END nome_projeto;

ARCHITECTURE logica OF nome_projeto IS
BEGIN
    SAIDA<=IN1 AND IN2;
END logica;