Sem descrição.
11/06/2025
Publico
Conversor 7 seg
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY conv_bin_dec IS
PORT (
entrada: IN std_logic_vector(3 downto 0);
saida_7seg: OUT std_logic_vector(6 downto 0)
);
END conv_bin_dec;
ARCHITECTURE logica OF conv_bin_dec IS
BEGIN
PROCESS(entrada)
BEGIN
CASE entrada IS
WHEN "0000" => saida_7seg <= "1000000";
WHEN "0001" => saida_7seg <= "1111001";
WHEN "0010" => saida_7seg <= "0100100";
WHEN "0011" => saida_7seg <= "0110000";
WHEN "0100" => saida_7seg <= "0011001";
WHEN "0101" => saida_7seg <= "0010010";
WHEN "0110" => saida_7seg <= "0000010";
WHEN "0111" => saida_7seg <= "1111000";
WHEN "1000" => saida_7seg <= "0000000";
WHEN "1001" => saida_7seg <= "0010000";
WHEN OTHERS => saida_7seg <= "0000110";
END CASE;
END PROCESS;
END logica;Toplevel
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY conversor_ISSP IS
PORT (HEXO: OUT std_logic_vector(6 downto 0));
END conversor_ISSP;
ARCHITECTURE logica OF conversor_ISSP IS
signal conexao : std_logic_vector (6 downto 0);
signal conexao_in : std_logic_vector (3 downto 0);
component issp_vhdl is
port (
source : out std_logic_vector(3 downto 0); -- source
probe : in std_logic_vector(6 downto 0) := (others => 'X') -- probe
);
end component issp_vhdl;
component conv_bin_dec IS
PORT (
entrada: IN std_logic_vector(3 downto 0);
saida_7seg: OUT std_logic_vector(6 downto 0)
);
END component conv_bin_dec;
BEGIN
u0 : component issp_vhdl port map (source => conexao_in, probe => conexao);
ul : component conv_bin_dec port map(conexao_in, conexao);
HEXO <= conexao;
END logica;