Sem descrição.
05/06/2025
Publico
tb_ex_1HZ.vhd
entity testbench1 is end;
library ieee;
use ieee.std_logic_1164.all;
architecture tb_ex_1HZ of testbench1 is
component ipcatalog
port(
CLOCK_50: in std_logic;
LED: out std_logic_vector(3 downto 0)
);
end component;
signal clk_1: std_logic := '0';
begin
cont: ipcatalog port map (CLOCK_50 => clk_1, LED => open);
estimulo : process
begin
wait for 10 ns;
clk_1 <= not clk_1;
end process estimulo;
end tb_ex_1HZ;
