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14/05/2025
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY clock IS
PORT (
clock_50: in std_logic;
ledr: buffer std_logic_vector(0 to 0)
);
END clock;
ARCHITECTURE logica OF clock IS
BEGIN
process (clock_50)
variable contador : natural range 0 to 50000000;
variable nivel_led : std_logic:= '1';
begin
ledr(0) <= nivel_led;
if rising_edge(clock_50) then
contador := contador + 1;
if contador = 50000000 then
contador := 0;
nivel_led := not nivel_led;
end if;
end if;
end process;
END logica;Refaça o exercício anterior acrescentando um pino de reset assíncrono. Quando o reset for pressionado, a saída deve ir a zero. Utilize LED[0] de saída e KEY[0] de reset. (quando pressionado, key = ‘0’)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY clock IS
PORT (
clock_50: in std_logic;
ledr: buffer std_logic_vector(0 to 0);
key: in std_logic_vector(0 to 0)
);
END clock;
ARCHITECTURE logica OF clock IS
BEGIN
process (clock_50, key(0))
variable contador : natural range 0 to 50000000;
variable nivel_led : std_logic:= '1';
begin
ledr(0) <= nivel_led;
if key(0) = '0' then
contador := 0;
nivel_led := '0';
elsif rising_edge(clock_50) then
contador := contador + 1;
if contador = 50000000 then
contador := 0;
nivel_led := not nivel_led;
end if;
end if;
end process;
END logica;Faça um PWM com a frequência de 5KHz e duty cicle de 10%. Utilize LED[0] de saída PWM e LED[1] de referência (nível 1).
Passos:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY clock IS
PORT (
clock_50: in std_logic;
ledr: buffer std_logic_vector(0 to 1);
key: in std_logic_vector(0 to 0)
);
END clock;
ARCHITECTURE logica OF clock IS
BEGIN
process (clock_50, key(0))
constant clock_division: natural := 10000;
variable contador : natural range 0 to clock_division;
variable nivel_led : std_logic:= '1';
constant dutty_time: natural := 10; -- 10%
constant active_limit : natural := (clock_division * dutty_time) / 100;
begin
ledr(1) <= '1';
ledr(0) <= nivel_led;
if key(0) = '0' then
contador := 0;
nivel_led := '0';
elsif rising_edge(clock_50) then
contador := contador + 1;
if contador = clock_division then
contador := 0;
end if;
if contador <= active_limit then
nivel_led := '1';
else
nivel_led := '0';
end if;
end if;
end process;
END logica;Faça um PWM com a frequência de 5KHz e 4 opções de duty cicle: 0, 15, 30 e 70%, utilizando 2 switch. Utilize LED[0] de saída PWM e LED[1] de referência (nível 1) e DIP Switch [1, 2] para a seleção.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY clock IS
PORT (
clock_50: in std_logic;
ledr: buffer std_logic_vector(0 to 1);
key: in std_logic_vector(0 to 0);
sw: in std_logic_vector(2 downto 1)
);
END clock;
ARCHITECTURE logica OF clock IS
BEGIN
process (clock_50, key(0))
constant clock_division: natural := 10000;
variable contador : natural range 0 to clock_division;
variable nivel_led : std_logic:= '1';
variable dutty_time: natural := 10; -- 10%
variable active_limit : natural := (clock_division * dutty_time) / 100;
begin
ledr(1) <= '1';
ledr(0) <= nivel_led;
-- calculando tempo de atividade
case sw is
when "00" => dutty_time := 0;
when "01" => dutty_time := 15;
when "10" => dutty_time := 30;
when "11" => dutty_time := 70;
end case;
active_limit := (clock_division * dutty_time) / 100;
-- Lógica
if key(0) = '0' then
contador := 0;
nivel_led := '0';
elsif rising_edge(clock_50) then
contador := contador + 1;
if contador = clock_division then
contador := 0;
end if;
if contador <= active_limit then
nivel_led := '1';
else
nivel_led := '0';
end if;
end if;
end process;
END logica;